1. Field of the Invention
The present invention relates to an addressing mapping circuit and, more particularly, to such a circuit capable of reducing the addressing operation by software in processing the structural and non-continuous addressing mapping.
2. Description of Related Art
Currently, the memory or peripheral device is accessed by a processor with a single fixed addressing mapping technique. That is, in designing hardware circuit, the accessable address of memory or peripheral is fixed. Some circuit utilizes incomplete decoding technique for decoding part of the address lines, such that peripheral or memory of the same type can correspond to different addresses. However, with such a technique, the data arrangements in different addresses are the same.
Some embedded CPUs have built-in address decoding circuit, which can be programmed to address the memory or peripheral. However, the accessed addresses are continuous.
As to the structural and non-continuous addressing mapping, software program is generally employed for the address manipulation in the conventional skill. Such a software manipulation usually requires to process the array data structure, which may greatly increase the loading of the processor. Therefore, there is a need for the above conventional addressing techniques to be improved.
One object of the present invention is to provide a multiple changeable addressing mapping circuit, which can process structural and non-continuous data by hardware, instead of a large amount software addressing operation.
Another object of the present invention is to provide a multiple changeable addressing mapping circuit which can increase the portability of program.
A further object of the present invention is to provide a multiple changeable addressing mapping circuit, which has a plurality of registers for determining the mapping functions.
According to one aspect, the present invention which achieves these objects relates to a multiple changeable addressing mapping circuit for converting an input logic address of a field array in a data array into an output physical address. The circuit comprises: at least an address mapper for process the conversion between the input logical address and the output physical address; a mapper selector for selecting an address mapper to output physical address; and a control and interface circuit for setting the base shift register, logical base register, field length register and recording length register, and controlling the address mapper and mapper selector. The address mapper comprises: a base shift register for recording a starting physical address of the field array to be mapped; a logical base register for recording a starting logical address of the field array to be mapped; a field length register for recording the length of a field; a recording length register for recording the length of the array; a subtracter for subtracting the input logic address from a logical base address stored in the logical base register; a division/remainder generator for dividing output value of the subtracter by a field length stored in the field length register 23; a multiplier for multiplying the array length of the record length register by a quotient of the division/remainder generator; and an adder for adding a starting physical address stored in the base shift register, a remainder of the division/remainder generator and an output value of the multiplier together to have an output physical address.
According to another aspect, the present invention which achieves these objects relates to a multiple changeable addressing mapping circuit for converting an input logic address of a field array in a data array into an output physical address. The circuit comprises: at least an address mapper for process the conversion between the input logical address and the output physical address; a mapper selector for selecting an address mapper to output physical address; and a control and interface circuit for setting the base shift register, field length register and recording length register, and controlling the address mapper and mapper selector. The address mapper comprises: a base shift register for recording a starting physical address of the field array to be mapped; a field length register for recording the length of a field; a recording length register for recording the length of the array; a division/remainder generator for dividing the input logic address by a field length stored in the field length register 23; a multiplier for multiplying the array length of the record length register by a quotient of the division/remainder generator; and an adder for adding a starting physical address stored in the base shift register, a remainder of the division/remainder generator and an output value of the multiplier together to have an output physical address.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.